Novel fault-tolerant adder design for FPGA-based systems

Alderighi, MMAlderighiDAngelo, SSDAngeloASI Sponsor2020-09-172020-09-172001-01-01https://hdl.handle.net/20.500.13025/885Novel fault-tolerant adder design for FPGA-based systemsArticle Journalhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=93781954dcce088580fe1368eeaf99