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Novel fault-tolerant adder design for FPGA-based systems
Details
Novel fault-tolerant adder design for FPGA-based systems
Author(s)
Alderighi, M
DAngelo, S
ASI Sponsor
Date Issued
2001-01-01
URI
https://hdl.handle.net/20.500.13025/885
Journal
On-Line Testing
URL
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=937819